Waymo Is Driving on 5nm. Xiaomi Has Validated 3nm. Tesla Is Moving From 7nm AI4 to a Reported 2nm-Class AI5.

Three companies now have custom chips for autonomous driving at three different points between a design file and a working fleet.

• Waymo's purpose-built 5nm ASIC is already operating in its sixth-generation Driver. It delivers more than 1,000 TOPS at the sensor front end and sits inside a system supplied by at least seven named semiconductor partners.
• Xiaomi's XRING D100 has completed design and validation. It supports 160GB of unified memory and models up to 200 billion parameters, but Xiaomi names no vehicle or volume and targets commercial use in 2027.
• Tesla's AI5 completed final design in April and targets 50× total improvement over AI4. High-volume production is planned for 2027 across Samsung and TSMC.

The headline comparison can be normalised on one axis. Use the same five observable production gates for every chip: final design, physical silicon, named vehicle integration, road operation and passenger service. Waymo clears all five. Xiaomi and Tesla clear the first two.

This is an R40 comparison framework, not an industry certification or a judgement of eventual performance. “Silicon” means a physical chip or package has been publicly shown: Xiaomi operates D100 in the AI Cube, Tesla has shown an AI5 package after final design, and Waymo's part is deployed. A dash means the milestone has not been disclosed for that chip generation, not that no internal work has occurred.

The resulting difference is large and concrete: Waymo is three observable production gates ahead. Xiaomi and Tesla still need to name the vehicle configuration, validate the generation on public roads and put passengers behind it before their chips reach the same disclosed state.

Across performance and supply, the headline comparison remains three rankings. Xiaomi publishes the largest memory and model envelope, but no throughput. Tesla publishes the largest generational performance claim and has the broadest announced foundry plan. Waymo is the only one whose claimed performance is attached to a deployed system.

The performance figures still do not share a unit. Xiaomi is publishing model capacity, Waymo peak throughput for one stage of a larger system, and Tesla a relative target against its own previous generation. But production status and supply are directly comparable, and they show three very different paths to specialised EV silicon.

This is the chip comparison. We covered the cost of the vehicles carrying Waymo and Tesla's systems separately. Vehicle price is deliberately not the denominator here.

What an autonomous-driving chip has to do

Training and inference are different jobs. The enormous clusters used to train a driving model can take hours or days, distribute work across many machines and consume megawatts. The chip in the vehicle performs inference: it takes live sensor data, runs the trained model and produces an action before the world changes.

That makes five constraints more important than a generic benchmark.

1. Latency. A correct steering decision arriving late is an incorrect decision. The full path from sensor input to actuation has to stay inside a deterministic time budget.
2. Sustained throughput. The system processes several live streams continuously. A short benchmark burst is less useful than the work it can sustain at automotive temperature and power.
3. Memory. Model weights, activations and temporal context have to fit close enough to the compute that moving data does not become the bottleneck.
4. Power and heat. Every watt reduces range and becomes heat that has to be removed inside a sealed, vibrating vehicle.
5. Redundancy. A driverless system has to detect failures and continue safely. That may mean duplicated chips, duplicated computers or a separate fallback path.

TOPS captures only part of the second item, and only after the precision and operation being counted are specified. Parameter count mostly describes the third. A generation-on-generation multiplier can combine all five, but reveals none of them individually.

Production: one deployed, two aimed at 2027

The five-gate score above deliberately measures disclosure and deployment rather than semiconductor manufacturing jargon. Tape-out matters, but it does not tell a passenger whether the chip has survived vehicle integration. Passenger service matters, but it does not reveal yield. The test joins both halves by asking how far the physical design has travelled toward its intended use.

Waymo is already at the production stage

Waymo began fully autonomous operation with its sixth-generation Driver in February 2026 and opened Ojai vehicles carrying that system to public riders in August. Its Metro Phoenix integration operation is scaling toward capacity of tens of thousands of Driver installations a year.

That makes Waymo's ASIC the only chip in this comparison attached to a disclosed, operating sixth-generation autonomy system. “In production” does not mean Waymo fabricates it. It means the custom part has moved through design, fabrication, automotive qualification, system integration and driverless deployment—the gates Xiaomi and Tesla still have ahead.

Waymo does not disclose ASIC unit volume, yield or wafer allocation. The integration-capacity figure is for the complete Driver, not the number of chips coming off a foundry line, and the system uses more than one ASIC because its compute is duplicated for redundancy.

Xiaomi has validated D100, not deployed it

Xiaomi says D100 has completed design and validation and is scheduled for commercial use in 2027. That is more advanced than a paper architecture, but the company has not named a vehicle, start-of-production quarter, shipment target or foundry allocation.

The AI Cube proves that working D100 silicon exists in an engineering system. It does not prove automotive production readiness: a desktop prototype does not establish qualification under vehicle temperature, vibration, lifetime and functional-safety requirements.

Xiaomi's production bridge therefore has three missing steps in public: the first vehicle programme, automotive qualification in that programme and committed volume. Until those appear, “commercial use in 2027” is a target rather than a ramp.

Tesla has final silicon design and two foundries

Tesla completed AI5's final chip design in April 2026. Samsung-side tape-out was reported in July, and industry reporting says engineering samples are the 2026 objective while high-volume production remains a 2027 event. Tesla's own roadmap also places AI5 production in 2027 and AI6 in 2028.

This puts AI5 beside D100 and behind Waymo in the normalised production test. Tesla has shown an AI5 package and named its production partners, but AI5 is not yet the computer shipping in customer vehicles; AI4 is. A finished design is followed by foundry-specific physical design, tape-out, first silicon, bring-up, validation, packaging, automotive qualification and then yield ramp. Each stage can force a revision.

Process: 7nm in today's Tesla, 5nm at Waymo, 3nm at Xiaomi and 2nm at Samsung's AI5

Process node is the one technical label all three programmes publish or have credibly reported around them. It can be placed on one roadmap, provided the labels are not mistaken for literal transistor dimensions or a performance score.

On the node label alone, the sequence is clear: Tesla AI4 at 7nm, Waymo at 5nm, Xiaomi at 3nm and the Samsung implementation of Tesla AI5 at 2nm-class. The status column reverses it. The oldest two process labels are the ones operating in vehicles; the newest two are 2027 programmes.

That is not a coincidence. Automotive silicon values maturity differently from a phone or datacenter accelerator. A driving computer has to hold performance across temperature, vibration and a long service life, achieve automotive-quality defect rates and remain available for years. A mature node arrives with better-understood yields, packaging, reliability and supply. A leading node offers more transistor density and potentially better performance per watt, but its first production ramp carries more cost and yield risk.

What “2nm”, “3nm” and “5nm” do—and do not—mean

Modern node names are foundry product families, not measurements of one physical feature. Samsung 2nm, TSMC 3nm and an unspecified 5nm implementation cannot be converted into speed by dividing their labels. Transistor architecture, cell libraries, die size, clocks, voltage, memory interfaces and achieved software utilisation matter more than the integer.

The transistor architecture also changes across this table. Samsung's reported AI5 process is 2nm-class gate-all-around, a newer transistor structure than the FinFET generations commonly associated with 7nm and 5nm. That gives Samsung more control over current and leakage in principle. It does not tell us AI5's yield, sustained watts or automotive reliability in 2027.

Xiaomi's 3nm claim similarly establishes the fabrication generation, not the D100's throughput. It may use its density budget for more compute, more memory control, redundancy or lower power. With no die size, transistor count, TOPS or power disclosure, nobody outside Xiaomi knows which.

Waymo's 5nm choice looks less advanced on a roadmap and more advanced on a road. The part has already crossed the qualification and deployment gap. For an autonomous system, a node that works deterministically in public service is ahead of a smaller node that exists only in a 2027 plan.

Tesla is making the largest visible node transition: AI4 is reported on Samsung 7nm-class, while Samsung's AI5 implementation is reported for its 2nm-class Taylor process. But Tesla is dual-sourcing AI5, and the TSMC implementation's node has not been definitively disclosed. Writing “AI5 is a 2nm chip” without that qualifier collapses two physical implementations into the one Samsung has described.

Performance: three large numbers measuring different things

Xiaomi D100: model capacity without throughput

Xiaomi disclosed the broadest model envelope and the least about how quickly it runs.

XRING D100 is a 3nm smart-driving chip with a 20-core CPU, a 16-core NPU and support for as much as 160GB of unified memory. Xiaomi says it can deploy models with up to 200 billion parameters locally, that design and validation are complete, and that commercial application is planned for 2027.

The 160GB figure explains the 200 billion more than the process node does. Parameter count is principally a memory problem: at 8-bit precision, 200 billion weights alone require roughly 200GB; at 4-bit, roughly 100GB, before activations, caches and the rest of the software stack. A 160GB unified pool makes a heavily quantised model of that scale plausible without claiming that the chip evaluates every parameter on every driving frame.

The arithmetic also shows why “supports a 200B model” is not a speed specification. It says nothing about tokens or frames per second, memory bandwidth, achieved utilisation or latency. A storage device can hold a large model and run it slowly; an accelerator with less memory can run a smaller specialised model much faster.

Xiaomi disclosed no total TOPS, memory bandwidth, power budget, precision basis, chip cost or first vehicle. It also did not say whether D100 runs the entire driving stack or shares work with another processor.

What it did reveal is strategic position. Xiaomi's EVs currently rely mainly on Nvidia Thor, after using Orin. D100 moves the company from buying the central driving computer to co-designing silicon with its own models, sensors and vehicle electronics. Reuters reports that TSMC will manufacture the chip, although Xiaomi did not identify the foundry in its technical disclosure.

The specialisation is therefore vertical integration with a very large local memory envelope. Whether the result is cheaper, faster or simply capable of running a larger model is still undisclosed.

Waymo: 1,000 TOPS before the driving brain

Waymo published the largest absolute compute number and the clearest boundary around it.

Its purpose-built 5nm ASIC delivers more than 1,000 TOPS, but Waymo states exactly where those operations occur: the chip processes the “massive influx of raw data before it reaches our core ML brain.” It extracts and fuses information from lidar, radar and camera streams, including temporal denoising for low-light perception, then feeds a separate purpose-built inference engine.

That distinction is the article. The 1,000 TOPS is not the total Waymo Driver and does not measure the part that chooses a trajectory. It is the compute required to turn a high-bandwidth, multi-modal sensor field into something the driving model can use.

The sixth-generation sensor suite contains 13 cameras, four lidar and six radar. Waymo says its latest system processes thirteen high-resolution camera streams simultaneously and in real time. Unlike a conventional image processor, the ASIC also has to align different sensor types in space and time, preserve low-light detail and feed later models with deterministic latency.

Waymo optimises the full computer around three requirements:

• Responsive: onboard decisions within milliseconds, with pixels-to-actuation latency treated as the system output.
• Ruggedised: continuous operation under vibration, shock and extreme temperature, integrated with the vehicle's liquid-cooling loop.
• Redundant: two independent compute engines run full parallel workloads, with either able to take over.

The custom ASIC is one component in a heterogeneous computer. Waymo still names AMD, Nvidia, Micron, Samsung, Sandisk, Socionext and TSMC as partners. Its move to custom silicon is specialised rather than total: own the front end whose workload is unique to Waymo's sensors, and continue buying merchant CPUs, GPUs, accelerators and memory where the wider market can supply them.

Waymo also gives no whole-system TOPS, power budget, memory capacity or ASIC cost. Its 1,000-plus figure is precise about the stage and silent about the complete machine.

Tesla AI5: a relative number for the whole inference direction

Tesla publishes neither a parameter ceiling nor an absolute AI5 TOPS figure. It publishes a target against AI4:

• 10× raw compute
• 9× memory capacity
• 5× hardened block quantisation and softmax performance
• 50× total improvement over AI4

Tesla completed the final AI5 chip design in April 2026 and plans production in 2027; AI6 is planned for 2028. The company describes both as in-house inference chips for autonomy, and describes AI5's ramp as coinciding with Robotaxi and Optimus. That already makes AI5 broader than a single vehicle sensor processor.

The most revealing number is not 50×. It is the 5× hardened block quantisation and softmax line. Quantisation reduces the number of bits used for model weights and operations; softmax is a recurring operation in attention-based neural networks. Hardening both into silicon means Tesla is not merely adding generic arithmetic units. It is turning operations its own models perform repeatedly into fixed hardware paths.

That is the same co-design logic as an application-specific chip in a datacenter: measure the workload, identify where the model spends time and data movement, then devote silicon directly to it. Tesla's public description of its FSD chip team says the goal is maximum neural-network performance per watt, with the chip validated and brought into mass production in Tesla vehicles.

The 50× figure still cannot be compared with Waymo's 1,000 TOPS. Tesla calls it “total improvement”, not raw compute; raw compute is one of its inputs and rises 10×. Nor can it be compared with Xiaomi's 200-billion-parameter ceiling, because Tesla does not publish AI4's or AI5's absolute memory capacity in the same disclosure. The base values behind every multiplier remain private.

Tesla's specialisation is the recurring operations of its end-to-end vision and planning models, optimised for performance per watt and designed to reach a very large installed fleet. The metric it publishes is a roadmap, not a benchmark.

Three architectures, not three scores

Put the disclosures on the jobs they describe and the comparison becomes coherent.

Xiaomi is describing what can fit. Waymo is describing how much front-end arithmetic one stage can perform. Tesla is describing how far its next generation moves from its own current baseline.

Even the word “chip” hides a scope problem. Waymo's figure covers ASICs dedicated to the sensor front end inside a larger heterogeneous, duplicated computer. Tesla's AI5 is presented as the next inference processor for autonomy and Optimus. Xiaomi has not drawn the boundary around D100's responsibility at all.

This is why process nodes do not settle it either. A 3nm chip is not automatically faster or more efficient than a 5nm chip at a different workload. Die area, clocks, memory interfaces, precision, packaging, redundancy and software utilisation decide what the process delivers. Node labels are useful manufacturing context, not a driving benchmark.

Supply: single-source visibility, a broad merchant stack and dual foundries

Xiaomi replaces Nvidia with a TSMC dependency

Xiaomi's current driving stack mainly uses Nvidia Thor, after Orin. D100 internalises the chip design and can remove dependence on Nvidia's product roadmap and supplier margin. It does not internalise fabrication.

Reuters reports that Xiaomi contracted TSMC to manufacture the 3nm D100. No second foundry, packaging partner, memory supplier or committed capacity has been disclosed. TSMC is therefore the only named production source, not necessarily the only one Xiaomi will ever use.

That is vertical integration at the design layer and concentration at the manufacturing layer. Xiaomi gains control of the architecture while moving the critical external dependency from Nvidia's finished processor to TSMC's advanced-node wafers. With 160GB of unified memory, the undisclosed memory and packaging supply may matter almost as much as the logic die.

Waymo owns one specialised layer and buys the rest broadly

Waymo names AMD, Micron, Nvidia, Samsung, Sandisk, Socionext and TSMC as partners around its compute system. The list spans general compute and acceleration, memory and storage, ASIC design and foundry capacity, although Waymo does not map each company to a specific component.

This is the broadest disclosed supplier set and the least vertically integrated manufacturing model. Waymo owns the workload definition, ASIC architecture and system co-design; specialist vendors supply the pieces. The advantage is access to several best-in-class roadmaps. The cost is a larger bill of materials and more interfaces to qualify and coordinate.

Its custom ASIC reduces component count by pushing more front-end processing into purpose-built silicon, but it does not replace the merchant stack. Waymo explicitly names Nvidia and AMD in the same computer whose custom chip receives the headline.

Tesla dual-sources AI5 and is building a research fab

Tesla plans slightly different physical versions of AI5 from Samsung and TSMC, with software intended to run identically on both. Samsung already manufactures AI4. AI5's dual-foundry plan is the clearest attempt here to create capacity and resilience at the wafer level rather than rely on one advanced-node source.

Dual-sourcing a leading custom chip is difficult. Each foundry has different process rules, libraries and packaging choices, so Tesla is effectively qualifying two physical implementations of one architecture. That adds engineering cost but creates leverage against yield problems, geographic disruption and insufficient allocation at either supplier.

Tesla is also building a Research Fab at Gigafactory Texas and says it is expanding into semiconductor fabrication to secure sufficient, resilient supply. The wording matters: the disclosed facility begins as research capacity, not a replacement for Samsung or TSMC high-volume production. The current AI5 plan remains foundry-dependent even as Tesla tries to learn the manufacturing layer itself.

The supply comparison is therefore clean: Xiaomi has one reported foundry and many undisclosed dependencies; Waymo spreads a heterogeneous system across a named merchant ecosystem; Tesla is attempting dual-foundry production while adding internal research fabrication.

The missing common denominator

A real comparison would require each company to publish the same block of information:

No company publishes that full set. Xiaomi gives capacity without throughput. Waymo gives front-end throughput without the whole system. Tesla gives relative improvements without the baseline. Cost is undisclosed for all three chips.

The absence is understandable. These are competitive architectures, not standardised datacenter accelerators submitted to the same benchmark suite. The companies also control different portions of the stack, so a common test could flatter the component that one owns and omit the work another integrates elsewhere.

It still means any league table built from 200 billion, 1,000 TOPS and 50× is numerology.

Why every autonomy company eventually designs silicon

The three programmes converge on one economic idea even while their architectures diverge.

A merchant processor has to serve many customers and many workloads. It carries features an individual customer may not need and exposes its architecture through a general software layer. That flexibility is valuable early, when models and sensors change quickly and buying Nvidia is faster than designing a chip.

At scale, the trade reverses. A stable workload repeated across hundreds of thousands of vehicles rewards specialisation:

• Delete general-purpose circuitry the model does not use.
• Put common neural-network operations into hardened blocks.
• Move memory closer to compute and reduce data movement.
• Design sensor interfaces, cooling and redundancy as one system.
• Control the roadmap rather than wait for a supplier generation.
• Replace a supplier's gross margin with the fixed cost of internal design.

Tesla reached that decision first because it controls the vehicle, software and fleet. Waymo applies it selectively because its unique burden is the multi-modal sensor front end, while partners still supply the rest of the computer. Xiaomi is now making the same move from the position of an EV manufacturer that already owns the vehicle and models but still buys the driving processor.

The risk is the mirror image of the benefit. A custom chip freezes assumptions in silicon. If the model architecture changes faster than the chip cycle, the hardware can arrive optimised for yesterday's network. If vehicle volume misses, fixed development cost is spread across too few units. If a merchant supplier advances faster, vertical integration becomes an expensive way to trail the market.

That is the useful comparison between D100, Waymo's ASIC and AI5. Not which promotional number is largest, but which workload each company is confident enough to freeze into silicon.

What to watch

1. D100's first vehicle and production volume. This converts “commercial use in 2027” into a manufacturing plan.
2. D100's TOPS, memory bandwidth and power. These are the missing performance numbers between 160GB and a usable driving computer.
3. Xiaomi's memory and packaging suppliers. A 160GB unified architecture is a supply claim as much as a model claim.
4. Waymo ASIC volume and foundry mapping. TSMC and Socionext are named partners, but Waymo does not identify their exact roles or its wafer capacity.
5. Waymo's whole-system performance. The ratio between the 1,000-plus-TOPS front end and separate core inference engine would show where compute goes.
6. AI5 first silicon, yield and foundry split. Dual sourcing is only resilience once both versions qualify and ramp.
7. AI5's absolute baseline and sustained watts. Tesla's 10×, 9× and 50× targets still need AI4 values and a power envelope.
8. The next production gate. A named D100 or AI5 vehicle would move either chip from 2/5 to 3/5 on the common test; road operation and passenger service would still remain.
9. The TSMC AI5 node. Samsung's 2nm-class implementation is reported; Tesla has not published a complete foundry-by-node table for the second version.

Sources and provenance. The five-gate test is R40's framework. D100's 3nm process, specifications and 2027 timing are Xiaomi claims carried by CnEVPost; TSMC manufacture is Reuters reporting. Waymo discloses its 5nm ASIC, deployment, performance and suppliers but does not assign TSMC to that specific chip. Tesla discloses AI5's performance targets, final design and 2027 plan; AI4's Samsung 7nm-class production, Samsung's 2nm-class AI5 tape-out and the dual-foundry implementation are industry-reported. The TSMC AI5 node is undisclosed. Node names are foundry families, not physical dimensions or benchmarks. No company publishes comparable sustained performance, power, cost, yield or volume.