Nvidia reportedly told major customers that AI-server prices will rise more than 15% as memory costs surge. That points opposite to the 1% quarterly rack-price decline in our Nvidia model, though it is not yet clear whether this is a margin-neutral cost passthrough.
Nvidia reportedly told major customers that AI-server prices will rise more than 15% for systems shipping early next year, including Vera Rubin and Grace Blackwell configurations. Trade reports attribute the increase to sharply higher server-memory costs, with HBM4 and high-capacity LPDDR5X making memory a much larger share of a rack's bill of materials. The exact figures vary widely across secondary sources, so the durable observation is the direction: a cost line that had been expected to fall is rising enough to reach customer pricing.
That directly contradicts an input in our Nvidia model. The data-center compute vertical uses an NVL72-class rack price of $3.0 million and assumes that price declines 1% every quarter because performance per dollar improves and custom ASIC competition accelerates the trend. A one-off 15% step to $3.45 million, with the old decline still in place, adds about $26 per share to the modelled base value. Holding price flat instead of cutting it 1% a quarter adds about $32. Applying both changes adds roughly $63 per share. The continuing drift matters more than the first price increase.
The crucial ambiguity is margin. If Nvidia passes SK hynix and other suppliers' higher memory costs through at roughly zero incremental margin, Nvidia's revenue per rack rises while unit economics are protected rather than improved. For memory suppliers, however, the passthrough is direct evidence that the price cycle is strong enough to change the cost of an entire AI system. It also shows that customers have not yet responded by cutting HBM content or accelerator orders.
The model should retain the pricing sensitivity but wait for direct Nvidia commentary before changing its base case. For SK hynix, the more immediate conclusion is that extraordinary memory pricing is no longer confined to supplier filings: it is visible in the invoices paid by the next layer of the AI stack.
Apple has reportedly tested CXMT memory for China-market devices, but political approval and tight allocation remain obstacles. CXMT being sold out while earning a 48.7% March-quarter net margin weakens the near-term thesis that Chinese supply is already dumping memory and ending the cycle.
Apple has reportedly tested CXMT memory for iPhones and MacBooks intended for China as the AI buildout tightens component supply. The effort is politically difficult: Apple has sought US government clearance, while a bipartisan group of senators asked the company to rule out Chinese memory entirely. The practical obstacle may be just as important. CXMT's 2026 production is reportedly heavily committed, with domestic customers including ByteDance, Tencent and Xiaomi receiving priority. Apple may be willing to qualify a politically radioactive supplier and still find little incremental capacity available.
That matters for the memory-cycle debate. The common bear case says Chinese entrants eventually flood the market with low-priced bits, break incumbent discipline and end the shortage. CXMT's recent economics and allocation behaviour point in the opposite direction for now. Its March-quarter net margin was approximately 48.7%, up sharply from 2025, and reports describe the company as sold out rather than discounting excess output. A supplier earning scarcity margins and rationing capacity to domestic customers is participating in the cycle, not yet ending it. Apple's search for a second source is demand-side evidence that the shortage is real enough to outweigh substantial political and supply-chain risk.
The conclusion should stay time-bound. Testing does not mean Apple has secured meaningful volume, and reports differ between an outright lack of supply and CXMT refusing Apple's requested pricing. Chinese capacity can still become the source of a future glut as new fabs arrive. What the current evidence weakens is the claim that this glut is already here. Right now CXMT appears capacity-constrained, profitable and domestically prioritised—the opposite conditions from a dumping-led cycle break.
· Bloomberg via LiveSquawk · negative
SK hynix and Samsung are reportedly preparing more than $200B of shareholder returns while memory makers approve record fab spending. When rising prices fund both distributions and capacity, capital discipline may no longer constrain the next supply cycle.
SK hynix may add at least $130 billion of shareholder returns through 2027, according to a JPMorgan note reported by Bloomberg, while Samsung is separately reported to be planning roughly $72–80 billion. The important detail is the policy change: SK hynix is said to have lifted its commitment from up to half of cumulative 2025–2027 free cash flow to more than half. These figures remain estimates and press reports rather than completed distributions, but they describe an industry generating extraordinary cash.
The same boards are also approving extraordinary capacity. SK hynix authorised about ₩54.3 trillion of new fabs shortly before a ₩40 trillion buyback, with first-half capex up 73% and new production expected around 2028. Micron has outlined more than $250 billion of US investment through 2035, including a $50 billion Boise buildout whose second fab is scheduled for late 2028. That date matches the supply year in our Micron bear case. The cycle is currently profitable enough to fund both record distributions and record construction rather than forcing a choice between them.
That is what makes the news a warning rather than a celebration. Memory prices and Korean semiconductor exports are still rising sharply, so capacity decisions are being financed at the strongest point in the cycle and will arrive years later. Past cycles broke when high returns removed the constraint on new supply. The honest counterargument is that returning more than half of free cash flow leaves less cash for fabs and may itself demonstrate discipline. The decisive check is therefore whether capex rises alongside the payout policy. Current SK hynix guidance suggests it does.
The headline numbers need care. JPMorgan's $130 billion may describe capacity to return cash rather than a formal plan, Samsung is not tracked in our data, and per-kilogram trade prices are distorted by product mix. The durable signal is the combination: cash returns are expanding, fab commitments are expanding, and the new supply has a 2028 delivery schedule. Discipline has not necessarily broken, but it is no longer imposed by a shortage of capital.
· PolymarketMoney and UBS commentary via X · negative
Cathie Wood reportedly avoids memory stocks because inference chips may engineer out HBM, while UBS argues token economics are becoming more memory-driven. The dispute turns on HBM bits per accelerator—not accelerator demand alone.
A reported Cathie Wood comment says inference chips are beginning to engineer out high-bandwidth memory, while UBS argued in the same week that AI token economics are becoming increasingly driven by memory rather than compute. These are opposing claims about the same variable. If inference hardware shifts toward larger on-package caches, more SRAM or lower-precision formats, bandwidth required per token could fall even while accelerator shipments keep rising. The memory shortage could then ease without a single new fab.
The stress test is HBM content per accelerator, not accelerator unit growth. Current memory models largely assume a bandwidth-hungry world, and most bear cases focus on future supply. An attach-rate shock attacks demand instead. Near-term take-or-pay arrangements may delay the income-statement effect by protecting contracted volumes and floor prices, leaving the uncontracted book to absorb the change first. That would make an architectural shift a valuation event before it became a revenue decline.
The counterargument is that model weights still need to reside somewhere and that cheaper bandwidth per token can stimulate enough additional inference to increase total bits consumed. Shipping systems such as wafer-scale processors can reduce dependence on HBM for some workloads, but one architecture is not an industry trend. The evidence needed is concrete: HBM stack counts and capacity across accelerator generations, examples of deployed inference chips that reduce external-memory content, and token-level benchmarks that separate bandwidth constraints from compute constraints. Until those exist, “engineer out HBM” is a useful failure condition for the thesis, not an established collapse in demand.