← NVIDIA Corporation

Weekly notes

NVDA on the radar · as of 2026-W34

· Bloomberg via StockMKTNewz · neutral

Nvidia reportedly told major customers that AI-server prices will rise more than 15% as memory costs surge. That points opposite to the 1% quarterly rack-price decline in our Nvidia model, though it is not yet clear whether this is a margin-neutral cost passthrough.

Nvidia reportedly told major customers that AI-server prices will rise more than 15% for systems shipping early next year, including Vera Rubin and Grace Blackwell configurations. Trade reports attribute the increase to sharply higher server-memory costs, with HBM4 and high-capacity LPDDR5X making memory a much larger share of a rack's bill of materials. The exact figures vary widely across secondary sources, so the durable observation is the direction: a cost line that had been expected to fall is rising enough to reach customer pricing. That directly contradicts an input in our Nvidia model. The data-center compute vertical uses an NVL72-class rack price of $3.0 million and assumes that price declines 1% every quarter because performance per dollar improves and custom ASIC competition accelerates the trend. A one-off 15% step to $3.45 million, with the old decline still in place, adds about $26 per share to the modelled base value. Holding price flat instead of cutting it 1% a quarter adds about $32. Applying both changes adds roughly $63 per share. The continuing drift matters more than the first price increase. The crucial ambiguity is margin. If Nvidia passes memory cost through at roughly zero incremental margin, revenue per rack rises while unit economics are protected rather than improved. Treating all of the higher price as profitable revenue would overstate fair value. It also matters whether the model's $3.0 million base is still appropriate for a new rack generation before changing the drift assumption. Nvidia's next earnings call should provide better evidence than a relayed headline. Even with those caveats, the report closes the loop between the memory and compute cycles. Record memory pricing has so far been discussed as supplier upside; this is the invoice reaching hyperscalers and neoclouds. The model should retain the sensitivity, but wait for direct company commentary before promoting the $63 scenario into the base case.

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· PolymarketMoney and UBS commentary via X · neutral

Cathie Wood reportedly avoids memory stocks because inference chips may engineer out HBM, while UBS argues token economics are becoming more memory-driven. The dispute turns on HBM bits per accelerator—not accelerator demand alone.

A reported Cathie Wood comment says inference chips are beginning to engineer out high-bandwidth memory, while UBS argued in the same week that AI token economics are becoming increasingly driven by memory rather than compute. These are opposing claims about the same variable. If inference hardware shifts toward larger on-package caches, more SRAM or lower-precision formats, bandwidth required per token could fall even while accelerator shipments keep rising. The memory shortage could then ease without a single new fab. The stress test for Nvidia and the memory suppliers is HBM content per accelerator, not accelerator unit growth. Current models largely assume a bandwidth-hungry world: more accelerators multiply demand for HBM stacks. An attach-rate shock breaks that relationship. It could also change Nvidia's system economics if a larger share of value moves into custom silicon, packaging or on-die memory. The counterargument is that model weights still need to reside somewhere, and cheaper tokens can stimulate enough additional inference to raise total memory demand even when each token uses less bandwidth. Near-term contracts may delay the financial effect. Micron has described take-or-pay arrangements with floor prices, binding volumes and substantial customer commitments. If an architectural change lands inside those terms, it may hit the uncontracted book first and appear as a valuation change before it becomes a revenue decline. The evidence needed is concrete: HBM capacity and stack counts across accelerator generations, whether any shipping inference product actually reduces external-memory content, and token-level benchmarks that separate bandwidth constraints from compute constraints. Until those exist, “engineer out HBM” is a useful failure condition for the thesis, not an established trend.

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